A bus is commonly employed to interconnect modules of a computer system and to transfer signals between them so that desired operations may be carried out by the system. It is also a key element whose characteristics, e.g., speed, have a major impact on the overall performance of the system. In a synchronous computer system having a bidirectional bus, one of the signals transmitted to the modules is a clock signal used to control the timing of the desired operations. Specifically, the clock signal synchronizes the transfer and reception of data between the bus interface circuitry on each module.
For proper operation of the computer system, clock signals should arrive at the interface circuitry at the same time; otherwise, reliable data transmission is not ensured. For example, if a module receiving data is "clocked" later than others, the earlier-clocked modules may overwhelm the data before it is stored at its proper destination. The lack of simultaneity in reception of the clock signals at the modules, i.e., clock skew, directly increases the amount of time that the data must remain stable on the bus; this, in turn, increases the time required for each data transfer on the bus and, thus reduces the speed of the bus.
The amount of clock skew introduced into a computer system is a direct function of the variations in propagation delays among clock receiver chips of the system. A chip, i.e., a small piece of silicon on which integrated circuits are implemented, typically comprises transistors. In digital logic applications, a transistor switches "on", when saturated, and "off", when nonconducting, to generate full swings between power supply voltages. The resulting output voltage "signals" represent corresponding high and low states. Propagation delay, which affects the switching speed of the transistor, is highly dependent upon variations in the fabrication process of the chip. In addition, the applied voltage, the operating temperature environment and the loading conditions of the chip affect its performance.
For logic switching applications, the transistors of a chip are typically configured as inverter and buffer circuits. An inverter "inverts" the logic sense of a binary signal, while a buffer is used merely for signal amplification; it does not produce any particular logic function since the binary value of the output is the same as the binary value of the input. However, buffering of low-level signals with semiconductor chips to develop high-level digital pulse signals is very susceptible to propagation delay variations due to process, voltage, temperature and loading (PVTL) variations. Differences in propagation delay between clock "buffer" chips in a system directly translate into skew. Removing propagation delay, and thus delay differences, is not physically possible; however, adding delay is.
The problem of clock skew is addressed partly by employing a system clock source and distributing the clock signals to the respective modules. The distribution is accomplished in a manner such that the clock signals arrive essentially simultaneously at the modules. However, in each module the incoming clock signals must be processed, i.e., shaped, amplified and regenerated into multiple copies, before use by various circuits on the module. Such processing necessarily delays the signals; the delays can be expected to vary from module to module because of PVTL variations. These variations contribute significantly to clock skew and the present invention is directed to the reduction of the skew.
A particular approach to reducing process, voltage and temperature (PVT) inspired clock skew is disclosed in an article titled, VLSI PERFORMANCE COMPENSATION FOR OFF-CHIP DRIVERS AND CLOCK GENERATION, by Dennis T. Cox et al. of IBM from Proceedings of IEEE 1989 Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4. In general, the disclosed skew regulator uses an external precision clock to develop an accurate pulse. This pulse is introduced into a tapped delay line (five "odd" taps from a 287-inverter chain). The taps are monitored by latches which are closed at the falling edge of the pulse. A fast PVT condition causes the pulse to pass more of the taps, resulting in the storage of more zeros (widely spaced odd taps are used) in a PVT measurement latch, than a slow PVT condition. The resulting PVT measurement "word" is used to select a tap on an input clock buffer delay line to add propagation delay to fast chips and minimize delay on slow chips.
The above-described approach requires a separate clock source to operate a programmable sense element (PSE). The skew regulator is implemented on every device it services in the system. Tap selection on the measurement delay line is tailored to a specific process and the taps are not evenly spaced. The PSE stage measurement delay chain and the 5-stage clock delay line are not sized the same and, generally, do not track identically with all process variations. Specifically, relative, as opposed to absolute, measurement of clock propagation delay is performed.
Other prior attempts to control skew of an output clock signal with a input signal typically employ a phase locked loop (PLL). A PLL is a device which continually strives to track the frequency of an input signal. The frequency of a voltage controlled oscillator (VCO) signal is compared with that of the input signal using a phase comparator that produces an error voltage proportional to their frequency difference. This error voltage is used to control the frequency of the VCO. Specifically, filtering of the error voltage involves a trade-off determination between acquisition time, i.e., the time it takes to "lock" the frequency of the VCO to an average frequency of the input signal, and jitter, i.e., phase noise.
A problem with the PLL approach is that jitter is a major contributor to skew. In addition, replication of input and output circuitry in the PLL feedback path is needed for accurate phase tracking, while separate loops are required for each clock phase. Moreover, each PLL in the system contributes its own phase-offset error depending on VCO, filter and phase detector PVTL variations.
Therefore, it is among the objects of the invention to provide an "absolute" delay regulation technique that reduces clock skew.
Another object of the invention is to minimize the number of clock lines on a system backplane.
Yet another object of the present invention is to redistribute multiple copies of low skew clock signals to circuitry on a module.
Still another object of the invention is to provide as much time as possible during a limited bus cycle period to transmit data across a high-speed, bidirectional synchronous bus.